1. Field of the Invention
The present invention relates to a crystal oscillator providing a reference frequency to communication system, and more specifically, to a method for compensating temperature in the crystal oscillator.
2. Description of the Prior Art
In recent years, techniques for wireless communication equipments have been actively developed. The wireless communication equipment has a crystal oscillator to provide a reference frequency. The crystal oscillator for compensating temperature among those oscillators provides a constant reference frequency in regardless of variations of surrounding temperature. More researches have been conducted for the temperature compensator of the crystal oscillator in digital form for implementing high frequency accuracy and one chip, because analogue form has a disadvantage for a small-sized device.
Hereinafter, design of the crystal oscillator by prior art will be explained with reference to FIG. 1.
FIG. 1 shows a circuit for explaining a three-point crystal oscillator of the prior art. Referring to FIG. 1, the characteristics of the three-point crystal oscillator are determined by the three points of Colpitts, Pierce, and Clapp. Capacitors C1 and C2 change transconductance of the transistor M1 to frequency-dependent negative resistance. At this time, the negative resistance (−R) can be defined as equation 1 below.                               -          R                =                              g            m                                              ω              o              2                        ⁢                          C              1                        ⁢                          C              2                                                          [                  Equation          ⁢                                           ⁢          1                ]            
Crystal static capacitance C0 of the crystal oscillator is parallel connected from C1, C2, and −R. Therefore, the negative resistance shown in the portion of Lm, Cm, and Rm of the crystal 10 is smaller than that obtained by the equation 1. C1 and C2 are designed much bigger than C0 in actual design. The equation 1 can also be applied to expect minimum transconductance gmc to compensate loss due to Rm and to maintain oscillation.
The minimum transconductance gmc can be defined as equation 2 below.gmc=Rmω02C1C2  [Equation 2]
Rm is a motional resistance of a resonator. C1 and C2 must be the same for optimal tradeoff between required transconductance and frequency safety. This means that the required transconductance is proportional to a square of load capacitance and oscillation frequency to have resonance.
For the exact measurement of power consumption, it is very important to find not only minimum transconductance for starting oscillation but also oscillation amplitude in steady state. The oscillation amplitude needs to be exceeded above specific level at a local oscillator of a RF receiver. For example, 0 dBm is required to turn on/off a switch transistor of a mixer while minimizes noise. The oscillation amplitude must be big enough to drive a digital prescaler in a frequency mixer. The amplifier should have gain much higher than the oscillation frequency so that the amplification at behind stage of the oscillator is not efficient for normal power.
If the oscillation amplitude in steady state is taken into consideration, power consumption requirement can be formulated in different way other than determined only by start-up condition. The exact expression of steady state amplitude of the three-point oscillator implemented as a MOS transistor can be obtained by time domain analysis. M1 should be designed to have transconductance much higher than (√{square root over (3)}/√{square root over (2)})gmc in actual design. In this case, voltage swing across the gate of M1 is so big that it becomes turned off during each period of the oscillation. If duty cycle of current of M1 is α, equation 3 below can be applied to derive Vm that is oscillation amplitude in stead state.                     x        =                              cos            ⁡                          (              απ              )                                =                                                    V                T                            -                              V                B                                                    V              m                                                          [                  Equation          ⁢                                           ⁢          3                ]            
Referring to equation 3, VB means a DC biased voltage in steady state between the gate and source of the M1. And, VT is a threshold voltage of M1. According to the define of x as shown in equation 3, Vm that is oscillation amplitude in steady state can be derived as in equations 4 and 5.                               V          m                =                                                            4                ⁢                                  I                  o                                                            g                                  m                  ⁢                                                                           ⁢                  c                                                      ⁢                                                                                (                                          2                      +                                              x                        2                                                              )                                    ⁢                                                            1                      -                                              x                        2                                                                                            -                                  3                  ⁢                  x                  ⁢                                                                           ⁢                                                            cos                                              -                        1                                                              ⁡                                          (                      x                      )                                                                                                                                        (                                          1                      +                                              2                        ⁢                                                  x                          2                                                                                      )                                    ⁢                                                            cos                                              -                        1                                                              ⁡                                          (                      x                      )                                                                      -                                  3                  ⁢                  x                  ⁢                                                            1                      -                                              x                        2                                                                                                                          =                                                                      I                  o                                                  g                                      m                    ⁢                                                                                   ⁢                    c                                                              ⁢                              f                ⁡                                  (                  x                  )                                                      ≈                                                            I                  o                                ⁡                                  (                                      5                    +                    x                                    )                                                            3                ⁢                                  R                  s                                ⁢                                  ω                  0                  2                                ⁢                                  C                  1                                ⁢                                  C                  2                                                                                        [                  Equation          ⁢                                           ⁢          4                ]                                                      2            ⁢            β            ⁢                                                   ⁢                          I              o                                            g                          m              ⁢                                                           ⁢              c                        2                          =                                            (                                                g                  m1                                                  g                                      m                    ⁢                                                                                   ⁢                    c                                                              )                        2                    =                                                    g                2                            ⁡                              (                x                )                                      =                                                            9                  ⁢                  π                                2                            ⁢                                                                                          (                                              1                        +                                                  2                          ⁢                                                      x                            2                                                                                              )                                        ⁢                                                                  cos                                                  -                          1                                                                    ⁡                                              (                        x                        )                                                                              -                                      3                    ⁢                    x                    ⁢                                                                  1                        -                                                  x                          2                                                                                                                                                          (                                          2                      +                                                                        x                          2                                                ⁢                                                                              1                            -                                                          x                              2                                                                                                                          -                                              3                        ⁢                        x                        ⁢                                                                                                   ⁢                                                                              cos                                                          -                              1                                                                                ⁡                                                      (                            x                            )                                                                                                                )                                    2                                                                                        [                  Equation          ⁢                                           ⁢          5                ]            
In equation 5, x is a monotonic function of ratio between gm1 and gmc. When the ratio of gm1 and gmc changes from 1.225 to 10, x is rapidly rose from −1 to 0.7. In accordance with the equation 4, this results in 28% change of oscillation amplitude. When the ratio of gm1 and gmc is more than 10, the oscillation amplitude is not changed. When the transconductance of M1 is several times bigger than the threshold for oscillation, the transconductance contributes less to determine the amplitude of the oscillator in steady state. In this case, dominant parameters are a bias current proportional to Vm and a gmc inverse proportional to Vm.
Most oscillators are designed to have specific amplitude for oscillation. This means the amplitude can be adjusted to have high transconductance. Therefore, the duty cycle of the current in M1 is lower than 100%, and the equation 4 defines the value of Vm. A bias current is adjusted to a square of oscillation frequency to have same Vm in accordance with the equation 4.
The motional resistance of the high frequency crystal can be lower than that of the low frequency crystal. However, such reduction in Rs will be limited by on-resistance of switch of trimming network. Furthermore, the accuracy of the capacitor array limits the ability for scaling capacitors C1 and C2 in order to consume less power.
Hereinafter, the frequency compensation for the crystal oscillator in digital type will be described.
One of the requirements for the present oscillator design is the accuracy of oscillation frequency in a range of sub-ppm. The accuracy in a state of the crystal resonator not compensated is about ±50 ppm including difference due to a change from temperature and cutting angle. One method for compensating the oscillation frequency is to change the equivalent capacitance parallel- connected to the resonator. In the three-point oscillator, the equivalent capacitance is a shunt capacitance C0 that is parallel connected to C1 and C2. The capacitors C1 and C2 should be made a few times higher than the capacitor C0 for frequency stability. This means that a mount of change should be large to cover a wider compensation area. The oscillation frequency of such a circuit is given approximately by the equation 6 below.                               f                      o            +            c                          =                              1                          2              ⁢              π              ⁢                                                                    L                    m                                    ⁢                                                                                    C                        m                                            ⁢                                              C                        L                                                                                                            C                        m                                            +                                              C                        L                                                                                                                          ≈                                    1                              2                ⁢                π                ⁢                                                                            L                      m                                        ⁢                                          C                      m                                                                                            ⁢                          (                              1                +                                                      C                    m                                                        2                    ⁢                                          C                      L                                                                                  )                                                          [                  Equation          ⁢                                           ⁢          6                ]            
In the equation 6, Lm and Cm are each motional inductance and motional capacitance of a resonator. Meanwhile, CL is an equivalent load capacitance dominated by the C1 and C2. Fractional frequency variation due to the CL is the second term of parenthesis in the equation 6. This can be used as a method for compensating the crystal oscillator.
FIG. 2 shows not only crystal nominal characteristic but also characteristic limiting frequency deviation. The extremes are represented to +TR and −TR. In FIG. 2, x axis represents CB not CL. CB means a serial combination of C1 and C2 implemented as two banks. That is, when C1=C2, CB=0.5C1=0.5C2. CL is a parallel combination of C0 and CB. For example, frequency can be adjusted along the curve A in FIG. 2. In this case, highest value of unit capacitance in a capacitor array can be determined to achieve the compensating resolution of 0.2˜0.3 ppm in compensation area. In other example, the oscillation frequency can be compensated along the curve C. Since the curve C has the highest inclination among compensating curves, the smallest unit capacitance in capacitor array can be determined. When the smallest unit capacitance in capacitor array is used, more unit capacitors are needed to compensate along the curve A. Also, to have compensating area of 100 ppm in consideration of 20% error of MOS capacitor, 210 of unit capacitor is needed. When the capacitor array needs to be consisted of C1 and C2 for a fixed capacitance (that is required to remove negative resistance produced by the M1 even when a switch is turned off) and frequency compensation, the many unit capacitors become an obstacle for low power consumption.
In accordance with the equation 4, current consumption is proportional to the equivalent resistance that is serially connected to C1 and C2. Therefore, the on-resistance of the MOS switch forming the capacitor array must be taken into consideration to minimize power. When C1 serially connected to the equivalent resistance Rsw of all switches that are turned on as in FIG. 3a is regarded to consist of C11 that is fixed and C12 that can be varied, FIG. 3a can be changed to FIG. 3b, so that the relation between required current and C12 can be obtained. The equivalent resistance Rsw,eq in FIG. 3b is approximately related to the switch resistance. The equivalent resistance Rsw,eq can be shown in equation 7 below.                                           R                          SW              ,              eq                                ≈                                                    (                                                      C                    12                                                                              C                      11                                        +                                          C                      12                                                                      )                            2                        ⁢                          R              SW                                      =                                            (                                                C                  12                                                  C                  1                                            )                        2                    ⁢                      R            SW                                              [                  Equation          ⁢                                           ⁢          7                ]            
The on-resistance of a minimum-sized switch in a typical 0.6 μm CMOS technology is of the other of several kilo-ohms. To reduce the on-resistance, the width of the switch transistor should be sufficiently wide. However, the drain -and substrate capacitance, which affects the compensation accuracy when the switch turns off, becomes so large that the width of the gate cannot be made too wide. Not only the size of the switch but also C1 and C2 must be traded off between accuracy and power consumption.
How to organize compensating capacitor array also should be taken into consideration. The most immediate way is to organize binary weighted array connected by switches having binary weighted channel widths. However, monotonicity of the compensation curve is critical concern for terminal system design, so that the value of LSB (Least Significant Bit) capacitor becomes low to ensure sufficient matching accuracy. Alternatively, the capacitor array can be organized as a parallel arrangement of unit capacitors, and controlled by thermometer codes as shown in FIG. 4a. Increase in total compensating capacitance is achieved by adding a new unit capacitor, so that the monotonicity can be guaranteed in this case. However, a parallel array of unit capacitors requires not only many more switches but also additional decoding logic to realize the thermometer code. This does not lose monotonicity while reducing amount of the total compensating capacitance, but increase the overall silicon area. In application requiring only frequency stability, large C1 and C2 are not required, and inherent resonance frequency of the crystal is not required. Therefore, the size of C1 and C2 can be made several times higher than that of C0 to transform sufficient negative resistance generated by M1 into the series resonator loop of the crystal. Lower capacitance brings in low current consumption. Therefore, the parallel arrangement of the unit capacitor can achieve low power while keeping monotonicity. At the time of designing thermometer code, many unit capacitors within the capacitor array should be selected at the same time, which is different from the case of RAM device. Referring to FIG. 4b, to implement simultaneous selection without any wires, decoding logic by a row decoder and a column decoder must be separated from the four transistors in each switch site. A pass transistor logic of SW=(AR∩{overscore (CR)})∪(COL∩CR) is implemented by the four transistors. AR (Active Row) represents rows in which all unit capacitors are turned on, so that all unit capacitors in the row having AR as 1 becomes turned on even when a column is 0. CR (Current Row) represents the current row being selected, and acts as a moving cursor showing that some unit capacitance of the row are added to C1 and C2. The column decoder makes column as 1 and thereby shows the position up to which the row should be turned on. This enables it possible to distribute decoding logic and to reduce an amount of wiring. The parallel arrangement using the binary weighted arrangement and thermometer code had problems of monotonicity and large silicon area consumption, etc.